- Groundbreaking software can save time and costs for chipmakers by revealing problems early
- The tool leverages AI, machine learning, and digital twins to improve time to market
Driving the news: Fabtex™ Yield Optimizer is a new Semiverse® Solutions software solution specifically designed to improve yield for high volume manufacturing (HVM) at fabs.
- The groundbreaking software uses proven optimization techniques, virtual silicon digital twins, and inline fab data to reduce process variability.
Why it matters: Low yield from process-related failures takes time to resolve, delaying time to market. Fabtex can shorten this cycle and reduce costs by minimizing wafer testing and waste.
Fabtex works by leveraging the customer’s virtual silicon process and inline metrology data already available in SEMulator3D®, applying artificial intelligence and machine learning (AI/ML), and recommending a set of new inline metrology targets to improve yield, faster.
- It is believed to be the first tool in the industry to use a nominal virtual process model trained with fab data and AI/ML to recommend metrology target changes for yield improvement.
“If you can adjust your process window virtually without spending months running sequential experiments on physical wafers, you can save time to yield and improve time to market,” says Joseph Ervin, managing director of Semiverse Solutions in the U.S.
Better Yield Results from Fabtex
Semiconductor manufacturers use a standard yield improvement approach that relies on Pareto analysis to identify and address individual process-limited yield detractors one at a time, starting with those with the highest impact.
- This sequential, build-and-test method limits the progress of yield optimization and ultimately slows the speed at which technology can be released to the market.
- Frustratingly, adjusting one process to reduce a particular yield detractor can unintentionally lead to increases in yield losses elsewhere.
Because Fabtex uses machine learning and virtual silicon digital twins, the process optimization cycle can be accelerated.
- This approach allows engineers to efficiently identify and address multiple yield detractors at once by enabling rapid variability propagation and uncertainty quantification across complex process integration steps.
Fabtex Shows Significant Value in Real-World Case Studies
Using virtual silicon with wafer data has already demonstrated significant value with customers.
In one case, a leading device manufacturer was able to use a virtual silicon approach to correct systematic defects for a new product introduction (NPI) tape-out at HVM.
- If the NPI was run without correction, the defects would have impacted all the wafers inline until the end-of-line e-test, causing considerable scrap and time delay.
- Capturing and correcting defects early in NPI saved months of time and created a “first time right” chip delivery.
In a second case at another device manufacturer, Fabtex was applied to resolve a defect caused by a multiple process-step interaction. In this case, the technology integration was extremely complex, with many processes on a 3D structure.
- The interaction effects also occurred between many modules of the technology, from the very beginning of the process flow, all the way until the middle of line. These are extremely challenging issues to resolve across many process steps.
- The resulting process corrections eliminated the defect without introducing other systematic defects.
- Employing virtual silicon helped identify the most critical steps in the process flow and root causes that contributed to the defect. In addition, Fabtex gave a recommendation on how to correct the defect that was verified on silicon.
- The resulting process corrections eliminated the defect without introducing other systematic defects. This approach boosted the yield from this stubborn defect mode.
Bottom line: Using Fabtex can shorten the build/test iteration timeline by employing virtual processing and ML/AI, thereby reducing the need to process additional physical wafers and getting products to market faster.
1 Assumptions: Without digital twins: 10 silicon improvement iterations at 9 weeks per iteration; with digital twins: five silicon improvement iterations at 10 weeks per iteration.
