SCI Semiconductor is developing ICENI microcontrollers and processors that enforce memory safety directly in hardware using CHERI technology. Visit Astute Group at electronica 2026 to see the demonstration and explore an approach that tackles memory-access vulnerabilities inside the processor.
A software error can let code stray into memory it should not use. The consequences can include a system crash or a vulnerability that an attacker could exploit.
SCI’s approach puts rules around those memory accesses and has the hardware enforce them. CHERI, short for Capability Hardware Enhanced RISC Instructions, attaches bounds and permissions to memory references. These define where software can access memory and what it may do there.
The chips also support protected software compartments with tightly controlled access between them, helping contain the effects of a fault or compromise.
For teams designing systems for critical infrastructure and industry, memory safety is worth addressing from the outset.
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SCI is bringing CHERI from academic research into commercial chips and is a core supplier in the UK government’s Accelerated CHERI Adoption Programme.
Visit Astute at Messe München on 10–13 November, Hall C5, Stand 421, to discuss hardware-enforced memory safety and how our experts can help you assess it for your design. Book a meeting, or stop by to see the demo and have a coffee on us.
