Weebit Nano Limited, a leading developer and licensor of advanced memory technologies for the global semiconductor industry, has launched the Weebit Matrix™ In-Memory Compute (IMC) Research Program, designed to accelerate exploration of next-generation computing architectures. The program provides industry and academic researchers with a ReRAM-based hardware development kit for exploring and prototyping IMC algorithms and systems.
In modern AI workloads, moving data between the processor and memory has the potential to create significant performance and bandwidth bottlenecks, and to account for a substantial part of total energy consumption. IMC performs calculations directly within memory, reducing data transfers, improving speed and significantly lowering power consumption. IMC architectures, particularly those using non-volatile memories (NVMs) like ReRAM, are most appealing for AI inference applications, especially in edge and IoT devices.
Through the Weebit Matrix IMC Research Program, researchers can use the provided ReRAM-based platform to develop and test AI algorithms, investigate innovative programming methods, explore new AI and neuromorphic architectures, assess the potential power and performance gains, and more. Participating researchers will share their ReRAM-related findings and feedback with Weebit to help improve the technology and benefit the broader research community.
Weebit ReRAM could be a natural fit for such architectures, with ultra-low power consumption, scaling advantages, cost-efficiency, analog characteristics and ease of fabrication in the back end of the line (BEOL). It is also inherently radiation tolerant, making it a good fit for aerospace and defense, as well as medical applications.
A U.S.-based company specializing in radiation-tolerant AI hardware leveraged Weebit ReRAM to evaluate a next-generation, low-power AI accelerator for harsh environments, exploring neural-network processing directly within ReRAM arrays and benchmarking its performance against conventional GPU- and FPGA-based solutions. Based on its analysis, the company projected that, for a given AI inference workload, the in-memory-compute approach using Weebit ReRAM could consume approximately 80x less power than a GPU-based implementation, while also reducing latency by almost 100x. (1)
Coby Hanoch, CEO of Weebit Nano, said: “We’ve collaborated with partners on in-memory and neuromorphic computing research for years, including our first ReRAM-based spiking neural network demonstration with CEA-Leti in 2019. We’re seeing strong interest from companies and research institutes looking to explore how Weebit ReRAM can support such computing paradigms. This interest is already translating into engagements with industry players looking to participate in the research program.
“While there are still technical challenges to address before bringing a commercial IMC solution to market, this research program will allow us to collaborate with the research community, exchange knowledge and ideas, and help advance the technology.”
Simone Bertolazzi, PhD, Principal Analyst – Memory at market research and strategy consulting company, Yole Group, said: “Emerging NVMs like ReRAM are being heavily investigated for low-power edge AI-devices with near- and in-memory computing architectures. ReRAM combines non-volatility, scalability, low power, and analog computation capability, making it one of the most promising candidates for IMC. By enabling researchers to deeply investigate algorithms and architectures through its new IMC program, Weebit is helping to fuel innovation in this important area.” (2)
Kevin D. Johnson, neuromorphic AI technologist and researcher (3), said: “Weebit ReRAM opens up exciting possibilities for new computing architectures. My research has explored how its analog characteristics can enable calculations directly within memory, including applications in financial risk analysis and GPS signal manipulation detection. I’m particularly interested in combining ReRAM with other processing technologies to leverage their respective strengths. I look forward to using Weebit Matrix IMC to move beyond simulation, validate models against actual hardware, and evaluate system-level accuracy, latency and power consumption.”
Weebit Matrix IMC Kits
Weebit is initially offering the Weebit Matrix IMC platform as two research-focused packages:
- Weebit Matrix IMC Evaluation Package, including a direct-access evaluation board
- Weebit Matrix IMC Quick-Start Package, including a complete IMC board and FPGA subsystem as well as sample code
Each package includes chip samples (packaged dies), documentation, and an IMC board with a socket. The Weebit Matrix IMC chip features a 32×32 crossbar array architecture designed to support efficient multiply-accumulate (MAC) operations, vector-matrix multiplication, convolution processing, spiking neural networks (SNN) and analog computing.
Demonstration at electronica 2026
Weebit will demonstrate Weebit Matrix™ IMC at its booth at electronica 2026 (Hall C2, stand 637). To learn more or arrange a personal demonstration, visit https://www.weebit-nano.com/lp/electronica-2026.
Availability
The Weebit Matrix packages are available to qualified researchers. To apply with your research project, visit https://tinyurl.com/58j7bk7z. Requests will be evaluated to ensure alignment with the program’s research focus.
To learn more about the Weebit Matrix IMC Program, visit www.weebit-nano.com/matrix-imc.
