A Flash-based microcontroller with an integrated programmable logic block (CLB) is now available from Ersa Electronics. Although the type and quantity of peripherals on the devices in this family are the same, the number of external I/O pins vary based on the packaging. Compared to the CLCs included into previous Microchip PIC and AVR microcontrollers, the CLB in the PIC16F13145 series is a considerably larger and more complicated programmable logic block. Going forward, I believe we may see even larger CLBs in PIC16s. The PIC16F13145 microcontrollers additionally incorporate four CLCs for backwards compatibility.
Understanding how to link low-end microprocessor cores to run on 8 can be a bit tricky, so I think it’s vital to go over how to use the CLBs and show some sample usage before diving into the intricate internals of the PIC16F13145 chip. Somehow, a tiny 32-LUT programmable logic block that can process a million instructions per second is more beneficial than any of the individual parts. When the PIC16F13145 microcontroller’s CPU is too slow for the task at hand, or when you require some sort of basic parallel processing that surpasses the microcontroller’s multitasking capabilities, the CLB can be useful for implementing a tiny bit of hardware-level real-time processing.
Our early experimentation with FPGA chips was motivated by these kinds of uses, and Microchip has recently moved a small FPGA (though larger than the former CLC) to one of its microcontroller subfamilies. State machines or “high-speed” peripherals like stepper motor controllers, counters, quadrature decoders, software-driven signal muxes, and high-speed pulse-width modulators (PWMs) can be implemented with the CLB. When the CPU is in sleep mode, the CLB can make logical judgments, lowering the system’s overall power usage. The CLB’s outputs can be used to drive pins on external devices or to receive input from the microcontroller’s other peripherals.
The CLB has a striking resemblance to an FPGA’s programmable logic fabric. The logic cells in the original FPGA, the Xilinx XC2064, which was released in 1985, are extremely similar to the 32 basic logic elements (BLEs) that comprise the CLB. A D flip-flop and a 4-input LUT make up each BLE. 16 input selector latches are fed by a wide multiplexer, and these latches in turn control the CLB’s LUT inputs utilizing 40 distinct input signals derived from external input pins, bits from internal registers, and output pins from internal peripherals. The programmable edge detectors receive the outputs from all 16 input selector latches. These edge detectors can be configured to be completely bypassed or to be activated by negative edges instead of the default behavior of being triggered by positive edges. The eight CLB output bits are routed via eight more multiplexers to internal registers, external pins, or inputs from internal peripherals. To aid in the construction of a state machine employing the CLB, for instance, it also has a 3-bit hardware counter.
The switch matrix, configuration bits, and internal wiring of the CLB are not covered in Microchip’s documentation. You don’t have to be aware of them. It is not intended for these details to violate the designer’s intellectual property. Rather, CLB setup specifics are handled by the MPLAB Code Configurator (MCC), a free plug-in in the company’s MPLAB X integrated development environment (IDE) software, based on the designer’s schematic. The MPLAB IDE’s inbuilt schematic editor can be used to develop designs for the CLB of the PIC16F13145.
Until FPGAs become too big and complicated to implement diagrams, all FPGA designs were originally recorded using schematics. With the growing size of FPGAs in the early 1990s, schematic input was gradually replaced by HDL coding in Verilog or VHDL. By the early 2000s, when FPGA capacity was measured in hundreds of LUTs, my good buddy Robert Bielby remembers that schematic input for FPGA designs had mostly been replaced by text-based hierarchical HDL descriptions. (Bielby spent nearly 25 years working in the FPGA industry at Altera and Xilinx. Bielby and I are among the few engineers who can recall the days when FPGAs were defined by schematics.) More than thirty sheets of D-size paper were needed for the largest schematic drawing that Bielby could recall seeing. Though it dates back to the early days of electronics, Microchip’s schematic-based CLB design approach is still ideal for FPGAs with 32 LUTs. For the PIC16F13145 microcontrollers, creating 32-LUT CLBs is as easy as entering in a schematic. What is the largest FPGA design schematic you have ever seen, I wonder? Kindly respond to this question in the comments area.)
Basic symbols like D or JK flip-flops, 2- or 4-input multiplexers, 2-, 3-, and 4-input logic gates, and simple integer constants are used in the CLB’s schematic entries. (You might want to get some long-lost design secrets by consulting Don Lancaster’s TTL Cookbook.) The fundamental logic component of the CLB, the 4-input lookup table, can also be used directly. To enable the CLB to communicate with such on-chip peripherals, some of the microcontroller’s hardened peripherals can also be incorporated into the architecture. Through a register interface, which is shown on the schematic as bit-level inputs and outputs on the software-accessible input and output registers, the CLB can also communicate with the microcontroller’s CPU.
