Microchip has won a $50m project to develop the next generation of high reliability processor for space missions based on RISC-V technology with European engineers.
NASA’s Jet Propulsion Laboratory has selected Microchip to develop the High-Performance Spaceflight Computing (HPSC) processor that will provide at least 100 times the computational capacity of current spaceflight computers for all types of future space missions, from planetary exploration to lunar and Mars surface missions.
The radiation hardened, fault tolerant processor will be based on 12 instantiations of the X280 RISC-V core from SiFive and will be used in a series of ruggedised radiation tolerant single board computers.
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“Our current spaceflight computers were developed almost 30 years ago,” said Wesley Powell, NASA’s principal technologist for advanced avionics. “While they have served past missions well, future NASA missions demand significantly increased onboard computing capabilities and reliability. The new computing processor will provide the advances required in performance, fault tolerance, and flexibility to meet these future mission needs.”
Microchip will architect, design, and deliver the HPSC processor over three years, with the goal of employing the processor on future lunar and planetary exploration missions. The scalable, modular fault tolerant architecture will include significant research and development. A key element is to include the ability to shut down processing blocks to save power.
Microchip benefits from extensive space experience through its acquisition of Atmel and Microsemi and a space design team in France. Microsemi has a strong relationship with RISC-V core supplier SiFive and already has a range of radiation tolerant processors, networking and memory devices with a supply chain approved for NASA projects.
“Microchip’s HPSC processor is a high performance multi-core SoC platform architected with reliability, fault-tolerance, security and low power in mind. It will deliver comprehensive Ethernet networking, advanced AI/ML processing and connectivity support while offering unprecedented compute performance gain,” said Babak Samimi, VP of Microchip’s communications business unit.
“HPSC is a highly complex development and will involve Microchip engineers beyond North America, including Europe. Please note that the HPSC processor will be commercialized globally, and the European market needs for mission-critical edge computing is well aligned with the capabilities of our processor,” he said. “Additional product specification details will be provided at later date.”
The European Space Agency (ESA) has commissioned a similar programme, which is using the RISC-V open instruction set. SPARC and LEON designs are also still being used in space projects.
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“We are pleased that NASA selected Microchip as its partner to develop the next-generation space-qualified compute processor platform.” said Samimi at Microchip.
“We are making a joint investment with NASA on a new trusted and transformative compute platform. It will deliver comprehensive Ethernet networking, advanced artificial intelligence/machine learning processing and connectivity support while offering unprecedented performance gain, fault-tolerance, and security architecture at low power consumption,” he said.
“We will foster an industry wide ecosystem of single board computer partners anchored on the HPSC processor and Microchip’s complementary space-qualified total system solutions to benefit a new generation of mission-critical edge compute designs optimized for size, weight, and power.”
Microchip’s HPSC processor may be useful to other US government agencies for satellite systems, says NASA.
The processor could potentially be used for commercial systems on Earth that require similar mission critical edge computing needs as space missions and are able to safely continue operations if one component of the system fails. These potential applications include industrial automation, edge computing, time-sensitive ethernet data transmission, artificial intelligence, and even Internet of Things gateways, which bridge various communication technologies.