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Home Semiconductor

Silanna Semiconductor Adds Feature-Rich DSPs to Configurable Plural ADC Family

DSP integration in new 12- to 16-bit family of data converters reduces system load, improves SNR, and lowers system costs

Nimish by Nimish
January 6, 2026
in Semiconductor
Reading Time: 2 mins read
Silanna Semiconductor

Silanna Semiconductor DSPs

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SAN DIEGO, CA – Silanna Semiconductor today announced it has integrated a feature-rich DSP into its Plural™ family of high-speed, low-power ADCs.

All Plural analog-to-digital converters have been designed using the company’s proprietary ResolutionEngine™ data converter core, which enables the devices to be factory configured to create each SKU from a standard die. This approach allows Silanna to access greater economies of scale and deliver lower-cost devices with more secure supply chains, shorter lead times and no need to end-of-life customer configurations.

The integration of a DSP brings several functions on-chip, including decimation, digital down-conversion (DDC), interleaving, and IQ-mismatch correction. These would traditionally be undertaken by an FPGA and bringing them on-chip frees those resources, reduces system complexity and lowers the total system cost.

The Plural-DSP lineup includes 12-, 14-, and 16-bit resolution devices, with sampling rates ranging from 5 to 250 MSPS. They are intended for use in signal-chain and test-and-measurement applications across industrial, military, medical, communications markets.

“The new Plural-DSP ADC family builds on the cost and supply-chain-security benefits of our original line-up to let engineers also perform signal conditioning and channel correction directly on the converter,” said Randy Wayland, VP of Data Converter Products at Silanna. “This approach allows designers to optimize output bandwidth, improve signal-to-noise ratio, reduce system calibration overhead and better use existing resources to create additional functionality.”

Like the original lineup of Plural ADCs, the new DSP-enabled family of data converters combine a pipeline ADC core with on-chip reference and clock management circuitry and support LVDS and CMOS outputs. Additionally, the DSP-enabled ADCs include serial port control (3-wire SPI compatible), come in a range of package sizes from 5×5 to 9×9 mm, and have an operational temperature range of -40 to +85°C, with an extended temperature range available now.

The DSP Plural ADC product family and EVKs are available now through Silanna’s authorized network of distributors.

To register interest, download specifications, and order samples, please visit https://silannasemi.com/plural-adcs/.

Tags: DSPSilanna Semiconductor
Nimish

Nimish


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